The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a heteroepitaxial substrate as well as a fabrication process thereof.
Group III-V compound semiconductor materials generally have a characteristic band structure that facilitates high speed electron transfer because of large electron mobility pertinent to such semiconductor materials. Thus, Group III-V compound semiconductor materials are used extensively for high speed semiconductor devices such as MESFET, HEMT or HBT. Further, some of the group III-V compound semiconductor materials have a band structure that allows direct transition of carriers. Thus, the group III-V compound semiconductor materials are used also for optical semiconductor devices.
Generally, such a compound semiconductor device is formed on a wafer of a compound semiconductor material sliced from a single crystal ingot of the compound semiconductor material or on an epitaxial layer of the compound semiconductor material grown on a Si wafer. The former approach generally has a problem of increased cost due to the difficulty of growing a large diameter crystal ingot. Further, such a compound semiconductor wafer is heavy and brittle, and handling of such a wafer is substantially difficult as compared with the case of handling a Si wafer. This problem becomes particularly acute when forming semiconductor devices on a large diameter wafer.
The latter approach, on the other hand, is advantageous in the point that one can use a light and strong Si wafer that is produced by a well established process. As long as Si is used, a large diameter wafer is readily available at low cost. Thus, there are intensive studies for decreasing the fabrication cost of compound semiconductor devices by forming the devices on a layer of a compound semiconductor material grown epitaxially on a Si wafer.
Meanwhile, it is well known that there exists a large discrepancy between Si and a compound semiconductor crystal such as GaAs in terms of lattice constant and thermal expansion coefficient. As a result, one encounters various difficulties when growing a layer of a compound semiconductor material epitaxially on a Si wafer. It should be noted that there exists a discrepancy of about 4% in the lattice constant between Si and GaAs. Further, the thermal expansion coefficient of GaAs is about twice as large as that of Si. Thus, mere deposition of GaAs on a Si wafer does not provide a high quality GaAs layer suitable for the active layer of semiconductor devices.
In order to eliminate this problem and to grow a single crystal layer of a group III-V compound material upon a Si substrate with high quality, there is a proposal, as disclosed in the Japanese Laid-open Patent Publication 59-19762, to deposit a first GaAs layer on a Si substrate with a temperature of 400-500.degree. C., which is lower than the deposition temperature commonly used for GaAs, followed by an ordinary epitaxial deposition process of a second GaAs layer at a commonly used deposition temperature of about 700.degree. C. According to such a process, the first GaAs layer is deposited on the Si substrate with a state somewhat close to amorphous phase, wherein the first GaAs layer crystallizes subsequently upon deposition of the second GaAs layer at the temperature of about 700.degree. C. Thereby, the foregoing first and second GaAs layers collectively form a single crystal GaAs layer grown epitaxially on the Si substrate.
Further, Japanese Laid-open Patent Publication 1-290220 describes a similar process that further includes a step of depositing another, additional GaAs layer between the step of forming the first GaAs layer and the step of forming the second GaAs layer, wherein the step of depositing the additional GaAs layer is conducted at a temperature in the range of 550-600.degree. C. By providing the additional GaAs layer between the first and second GaAs layers, it is possible to reduce the defect density of the GaAs epitaxial layer thus formed.
However, such conventional two-step or three-step processes generally cause a problem in that undulation occurs on the surface of the heteroepitaxial layer grown on the Si substrate. Such an undulation is attributed to the formation of an island structure as a result of three-dimensional growth of the compound semiconductor crystal layer, rather than the desired, two-dimensional growth. Once formed, such an undulation on the heteroepitaxial substrate is transferred to the active layer of the semiconductor device that is formed on the heteroepitaxial substrate, and the operational characteristics of the semiconductor device is deteriorated seriously. In high speed devices such as HEMT that operates based upon the principle of high speed transfer of electrons in a two-dimensional electron gas, such an undulation of the active layer results in various unwanted effects such as carrier scattering.
Further, conventional heteroepitaxial substrates tend to show a problem of relatively low sheet resistance, in the order of 300-400/.quadrature.. Thus, such a conventional heteroepitaxial substrate suffers from the problem of inferior device isolation when used for carrying integrated circuits thereon. It is believed that such a decrease of the sheet resistance occurs at the time of a preheating process that includes an annealing process conducted in an arsine (AsH.sub.3) atmosphere, wherein such a preheating process is conducted for removing an oxide film from the surface of the Si substrate.
More specifically, As atoms in the arsine atmosphere cause a diffusion into the Si substrate as a result of the thermal annealing process conducted at a high temperature of typically about 1000.degree. C. The As atoms thus reached the Si substrate thereby cause a doping of the Si substrate to the n-type. In order to avoid such a problem of unwanted As doping of the Si substrate, it is conventionally proposed to conduct the preheating process in the H.sub.2 atmosphere rather than in the arsine atmosphere. However, such a process improves the sheet resistance only very little. Even according to such a process, the sheet resistance increases at best to the order of 600-700 .OMEGA./.quadrature.. The reason for this is believed to be that the compound semiconductor layer contains dislocations with very high density at the part thereof located in the vicinity of the interface to the Si substrate, and Si atoms in the Si substrate cause a diffusion into the compound semiconductor layer on the substrate along such dislocations. As a result, the compound semiconductor layer inevitably experiences doping, and the heteroepitaxial substrate cannot provide a sufficient device isolation.